x86: Fix register field encoding in VEX/EVEX prefix - #7564
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@Spencer-Comin This change should fix the issues with pdep/pext instructions |
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jenkins build xlinux, x32linux |
0xdaryl
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Nov 29, 2024
| void setSource2ndRegisterFieldInEVEX(uint8_t *opcodeByte) | ||
| { | ||
| uint8_t regNum = ((_fullRegisterBinaryEncodings[_registerNumber].needsRexForByte << 3) | _fullRegisterBinaryEncodings[_registerNumber].id); | ||
| uint8_t regNum = ((_fullRegisterBinaryEncodings[_registerNumber].needsRexPlusRXB << 3) | _fullRegisterBinaryEncodings[_registerNumber].id); |
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This change makes sense to me if you are updating the vvvv bits in P1. However, the code below seems to suggest that P1 is one byte beyond the opcodeByte, so now I am confused.
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Perhaps opcodeByte is poorly named. opcodeByte points to EVEX P1 in the instruction where vvvv bits are, not the literal opcode value.
uint8_t *evexP1 = opcodeByte + 1; should be P2
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Can you do that renaming now as part of this PR please?
added 2 commits
December 5, 2024 12:52
Signed-off-by: Bradley Wood <bradley.wood@ibm.com>
Signed-off-by: Bradley Wood <bradley.wood@ibm.com>
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Fixed the 32-bit encoding, improved naming. |
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Jenkins build xlinux,win,osx,x32linux |
0xdaryl
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Dec 7, 2024
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