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Z: Short circuit variable length array cmp helper - #7229

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hzongaro merged 1 commit into
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ehsankianifar:ShortCircuitVarLengthArrayCmpHelper
Feb 1, 2024
Merged

Z: Short circuit variable length array cmp helper#7229
hzongaro merged 1 commit into
eclipse-omr:masterfrom
ehsankianifar:ShortCircuitVarLengthArrayCmpHelper

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@ehsankianifar

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If the addresses of two arrays are equal, those two arrays are considered equal and we do not need to actually compare those arrays. In this PR, we modified the instructions for x86 and there was a discussion to do the same for other architectures. On Z, it is more complicated and depending on the conditions and expected response, several methods implement array compare.
This PR targets array cmp helper implementation when the length is variable. the arraycmpEvaluator calls arraycmpHelper when the length is variable or larger than 4k and requested response is unsigned.

@ehsankianifar

ehsankianifar commented Jan 16, 2024

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Instruction selection for this path:

 [     0x2aa17d56570]	                       LG      &GPR_0018, Parm[Parm  0<parm 0 L>] ?+0(GPR15)
 [     0x2aa17d743b0]	                       LG      &GPR_0020, Parm[Parm  1<parm 1 L>] ?+8(GPR15)
 [     0x2aa17d746f0]	                       L       GPR_0024, Parm[Parm  2<parm 2 I>] ?+16(GPR15)
 [     0x2aa17d748c0]	                       XGR     GPR_0017,GPR_0017	
 [     0x2aa17d74970]	                       Label L0016:	# (Start of internal control flow)	
 [     0x2aa17d74a30]	                       CLGRJ   &GPR_0018,&GPR_0020,Label L0017,BH(mask=0x8), 	
 [     0x2aa17d74b70]	                       AHI     GPR_0024,0xffff	
 [     0x2aa17d74c30]	                       BRC     BM(0x4), Label L0017	
 [     0x2aa17d942f0]	                       LR      GPR_0025,GPR_0024	
 [     0x2aa17d943a0]	                       SRA     GPR_0025,8
 [     0x2aa17d94460]	                       BRC     BH(0x8), Label L0019	
 [     0x2aa17d946a0]	                       Label L0018:	
 [     0x2aa17d94760]	                       CLC     #390 0(256,&GPR_0018),#391 0(&GPR_0020)
 [     0x2aa17d94820]	                       BRC     MASK7(0x6), Label L0020	
 [     0x2aa17d949a0]	                       LA      &GPR_0018,#392 256(&GPR_0018)
 [     0x2aa17d94b10]	                       LA      &GPR_0020,#393 256(&GPR_0020)
 [     0x2aa17d94bc0]	                       BRCT    GPR_0025,Label L0018	
 [     0x2aa17d94c80]	                       Label L0019:	
 [     0x2aa17d95030]	                       LARL    GPR_0026, &<LiteralPool Base Address>	 ; LoadLitPool
 [     0x2aa17db4a00]	                       assocreg
 [     0x2aa17db4470]	                       EX      GPR_0024,#396 0(GPR_0026)
 POST:
 {AssignAny:GPR_0017:R} {AssignAny:&GPR_0018:R} {AssignAny:&GPR_0020:R} {AssignAny:GPR_0024:R} {AssignAny:GPR_0025:R} {AssignAny:GPR_0026:R}
 [     0x2aa17db4ab0]	                       Label L0020:	
 [     0x2aa17db4b70]	                       BRC     MASK9(0x8), Label L0017	
 [     0x2aa17db4c30]	                       LGHI    GPR_0017,0x2	
 [     0x2aa17db4cf0]	                       BRC     MASK3(0x2), Label L0017	
 [     0x2aa17db4db0]	                       LGHI    GPR_0017,0x1	
 [     0x2aa17db5530]	                       assocreg
 [     0x2aa17db4f90]	                       Label L0017:	
 POST:
 {AssignAny:GPR_0017:R} {AssignAny:&GPR_0018:R} {AssignAny:&GPR_0020:R} {AssignAny:GPR_0024:R} {AssignAny:GPR_0025:R} {AssignAny:GPR_0026:R}
 [     0x2aa17db5690]	                       LGFR    GPR_0017,GPR_0017	
 [     0x2aa17db5cf0]	                       assocreg
 [     0x2aa17db5740]	                       retn    	
 POST:
 {GPR2:GPR_0017:R}

if (!isFoldedIf && needResultReg)
{
branchDeps->addPostCondition(retValReg, TR::RealRegister::AssignAny);
generateRRInstruction(cg, TR::InstOpCode::getXORRegOpCode(), node, retValReg, retValReg);

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in all code paths we need to init result register with zero

generateRRInstruction(cg, TR::InstOpCode::getXORRegOpCode(), node, retValReg, retValReg);
}

generateS390LabelInstruction(cg, TR::InstOpCode::label, node, cFlowRegionStart);

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The short circuit branch would always be the start of control flow.


if (maxLenIn256)
{
if (!isFoldedIf && needResultReg)

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we init result before short circuit. this code no longer needed.

{
if (isIfxcmpBrCondContainEqual)
setStartInternalControlFlow(cg, node, generateS390BranchInstruction(cg, TR::InstOpCode::BRC, TR::InstOpCode::COND_BL, node, compareTarget),
isStartInternalControlFlowSet);

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control flow always start before short circuit branch. This is no longer necessary.

@ehsankianifar

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@r30shah Please review and let me know if it looks good to you.

@ehsankianifar

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Tested for JDK8 (LoZ and zOS) Axxon 64179, test level.sanity, all tests pass
JDK11 (LoZ) Build #20215, test sanity.functional sanity.system sanity.openjdk, all tests pass.

Comment thread compiler/z/codegen/OMRTreeEvaluator.cpp Outdated
source1Reg,
source2Reg,
TR::InstOpCode::COND_BE,
isIfxcmpBrCondContainEqual ? compareTarget : cFlowRegionEnd);

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set needCC to false.

@ehsankianifar
ehsankianifar force-pushed the ShortCircuitVarLengthArrayCmpHelper branch 2 times, most recently from a535d71 to 0b82978 Compare January 23, 2024 15:00
@ehsankianifar

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After fixing jump instruction:
Tested for JDK8 (LoZ and zOS) Axxon 64612, test level.sanity, all tests pass
JDK11 (LoZ) Build #20268, test sanity.functional sanity.system sanity.openjdk, all tests pass.

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LGTM

@r30shah

r30shah commented Jan 24, 2024

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Jenkins build zos,zlinux

@r30shah

r30shah commented Jan 25, 2024

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@hzongaro Can I request you to merge this change if you are ok with it?

@hzongaro hzongaro self-assigned this Feb 1, 2024

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I think the changes look good. Thanks!

@hzongaro

hzongaro commented Feb 1, 2024

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x86-64 macOS failure is unrelated, of course, while relevant platform-specific testing passed. Merging.

@hzongaro

hzongaro commented Feb 1, 2024

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x86-64 macOS failure is unrelated, of course, while relevant platform-specific testing passed. Merging.

Actually, may I ask you to adjust the wording of the commit message to describe the change that's being applied? Maybe something like the following?

Add short circuit test of whether two array addresses are equal for
arraycmp.  This particular case handles unsigned result and variable
length or length greater than 4K.
Short circuit branching is added to the start of instruction sequence.

@ehsankianifar
ehsankianifar force-pushed the ShortCircuitVarLengthArrayCmpHelper branch from 0b82978 to 1f57d12 Compare February 1, 2024 15:28
@ehsankianifar

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Thanks @hzongaro for your help. I modified the commit message as you suggested. Please let me know if it looks good now.

@hzongaro

hzongaro commented Feb 1, 2024

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@ehsankianifar, thanks for updating the commit message. I don't know whether you've seen the Commit guidelines, but one thing they recommend is that lines in the body of the commit message shouldn't be longer than 72 characters, if possible. May I ask you to adjust the spacing so that each line is no longer than 72 characters?

@ehsankianifar
ehsankianifar force-pushed the ShortCircuitVarLengthArrayCmpHelper branch 2 times, most recently from 86feda1 to 049a571 Compare February 1, 2024 17:22
Add short circuit test of whether two array addresses are equal for
arraycmp. This particular case handles unsigned result and variable
length or length greater than 4K.
Short circuit branching is added to the start of instruction sequence.

Signed-off-by: Ehsan Kiani Far <ehsan.kianifar@gmail.com>
@ehsankianifar
ehsankianifar force-pushed the ShortCircuitVarLengthArrayCmpHelper branch from 049a571 to 47bc735 Compare February 1, 2024 17:24
@ehsankianifar

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Thanks @hzongaro for reminding me of that. I fixed the commit message.

@hzongaro
hzongaro merged commit 15e19bf into eclipse-omr:master Feb 1, 2024
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3 participants