Intel Sandy Bridge
Configuration
Intel i5-2400 (Sandy Bridge), 3.1 GHz, 32 nm.
- L1 Data cache = 32 KB. 64 B/line, 8-WAY. (Write-Allocate?), 2 * 16 Bytes read ports + 16 Bytes store port.
- L1 Instruction cache = 32 KB. 8-WAY. 64 B/line
- mOp Cache: 1.5k instructions, 8-WAY, 6 MOP / line
- 4 decoders, 16 bytes per cycle
- L2 cache = 256 KB. 64 B/line, 8-WAY
- L3 cache = 6 MB. 64 B/line, 12-WAY
- Load Buffers = 64
- Store Buffers = 36
- Line fill buffers (LFB) = 10
- RS = 54 items
- PRF Integer = 160 registers
- PRF Float = 144 registers
- ROB = 168 items
- RSB (return stack buffer) = 16 items ?
4 KB pages mode (64-bit Windows)
- Data TLB L1 size = 64 items. Miss penalty = 7. 4- WAY
- Instruction TLB L1 size = 64 items per thread.
- TLB L2 size = 512 items. . 4- WAY
- PDE cache = 32 items?
| Size | Latency | Description |
|---|---|---|
| 32 K | 4 | 5 | TLB + L1 |
| 256 K | 12 | +7 (L2) |
| 2 M | 36 | +17 (L3) +7 (L1 TLB miss) |
| 6 M | 46 | +10 (L2 TLB miss) |
| 64 M | 46 + 65 ns | + 65 ns (RAM) |
| ... | 58 + 65 ns | + 12 (PDE cache miss) |
- L1 Latency = 4 cycles is for direct pointers mode. The [R1 + R2*4] Load has 5 cycles latency.
- L3 Latency for cores 2 and 3 is 1-cycle smaller than L3 Latency for cores 1 and 4.
2 MB pages mode (64-bit Windows, 64-bit soft)
- Data TLB L1 size = 32 items.
- Data TLB L2 size = 512 items.
- Instruction TLB L1 = ? items
1 GB mode
- Data TLB L1 size = 4 items.
- Data TLB L2 size = 512 items.
- Instruction TLB L1 = ? items
MISC
Branch misprediction penalty = 14 cycles.
- 64-bytes range cross penalty = 5 cycles
- 4096-bytes range cross penalty = 24 cycles
- L1 B/W (Parallel Random Read) = 0.51 cycles per one access
- L2->L1 B/W (Parallel Random Read) = 2.5 cycles per cache line
- L2->L1 B/W (Read, 64 bytes step) = 2.1 cycles per cache line
- L2 Write (Write, 64 bytes step) = 6.70 cycles per write (cache line)
- L3->L1 B/W (Parallel Random Read) = 4.85 cycles per cache line
- L3->L1 B/W (Read, 64 bytes step) = 5.05 cycles per cache line
- L3 Write (Write, 64 bytes step) = 9.00 cycles per write (cache line)
- RAM Read B/W (Parallel Random Read) = 10 ns / cache line = 6400 MB/s
- RAM Read B/W (Read, 8 Bytes step) = 13700 MB/s
- RAM Read B/W (Read, 64 Bytes step) = 15200 MB/s
- RAM Read B/W (Read, 64 Bytes step - pointer chasing) = 11700 MB/s
- RAM Write B/W (Write, 4-64 Bytes step) = 9200 MB/s
http://www.7-cpu.com/cpu/SandyBridge.html
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